IPR Details
Nathan M Allen's General License Statement

Update this IPR disclosure
Submitted: April 12, 2026 under the rules in RFC 8179.

Note: Updates to IPR disclosures must only be made by authorized representatives of the original submitters. Updates will automatically be forwarded to the current Patent Holder's Contact and to the Submitter of the original IPR disclosure.

I. Patent Holder/Applicant ("Patent Holder")

Holder legal name Nathan M Allen

II. Patent Holder's Contact for License Application
Holder contact name Nathan M Allen
Holder contact email Nathan@interferencedr.com
Holder contact info

808-313-2473
Po box 5531
Hill,hi. 96720

III. Disclosure of Patent Information
i.e., patents or patent applications required to be disclosed by RFC 8179

A. For granted patents or published pending patent applications, please provide the following information:

Patent, Serial, Publication, Registration, or Application/File number(s)

Number: US64/031448
Inventor: NATHAN M ALLEN
Title: SYSTEM AND METHOD FOR SUBSTRATE INTEGRATED POST-QUANTUM CRYPTOGRAPHY (SI-PQC) VIA WAVE UNION SUBSTRATE TIMING AND PULSE-PHASE VERNIER CARRY
Date: 2026-04-11
Notes: I am the inventor of a method for SI-PQC that utilizes "Interference Ring Deletion" to physically nullify signals that do not match substrate-anchored timing. This technology addresses the "Negative Certification" state of legacy hardware like Co-Packaged Optics (CPO).

B. Does this disclosure relate to an unpublished pending patent application?:

Has patent pending Yes

IV. Statement

Statement

Licensing: I am disclosing this in fulfillment of a duty to inform the global network apparatus of this logic-based mitigation for quantum-scale temporal hijacking. All licensing is subject to the "Mandatory Technical Advisory and Reservation of Rights" included in the provisional filing.

V. Contact Information of Submitter of this Form

Submitter name Nathan M Allen
Submitter email Nathan@interferencedr.com

VI. Other Notes

Additional notes

PROVISIONAL APPLICATION

​INVENTOR: Nathan M Allen

PROVISIONAL APPLICATION FOR PATENT COVER SHEET
​I. INVENTION IDENTIFICATION
​Title of Invention: SYSTEM AND METHOD FOR SUBSTRATE INTEGRATED POST-QUANTUM CRYPTOGRAPHY (SI-PQC) VIA WAVE UNION SUBSTRATE TIMING AND PULSE-PHASE VERNIER CARRY
​II. INVENTOR INFORMATION
​Inventor Name: Nathan M. Allen
Residence Address: 16-1706 opeapea rd
City, State, Zip: pahoa,hi. 96778
Citizenship: United States
​III. CORRESPONDENCE ADDRESS
​Name: Nathan M. Allen
Address: po box 5531
Phone: 8083132473
Email: nathan@interferencedr.com
​IV. ENTITY STATUS
​Applicant asserts MICRO ENTITY STATUS under 35 U.S.C. § 123.
Note: Certification Form PTO/SB/15A is required to be filed alongside this cover sheet to qualify for the 75% fee discount.
​V. GOVERNMENT INTEREST
​Is there any US Government Interest in this application? [ ] Yes (If yes, specify agency and contract number)
[X] No
​VI. USE OF ACCOMPANYING DOCUMENTS
​Total Number of Pages in Specification: 3
Total Number of Sheets of Drawings: 0
​VII. SIGNATURE OF INVENTOR
​The undersigned inventor(s) believe they are the original inventor(s) of the subject matter which is described and claimed in the accompanying provisional application.
​Signature: Nathan M Allen
Date: April 6, 2026
Printed Name: Nathan M. Allen

​I. FIELD OF THE INVENTION

​The present invention relates to Physical Layer Security (PLS) and Non-Von Neumann Computing Architecture. Specifically, it defines a method for Substrate Integrated Post-Quantum Cryptography (SI-PQC) that utilizes the physical propagation properties of a communication medium to execute deterministic cryptographic logic.

​II. BACKGROUND: THE "NEGATIVE CERTIFICATION" OF LEGACY HARDWARE

​Current Post-Quantum Cryptography (PQC) standards rely on algorithmic software layers that are fundamentally decoupled from the physical hardware substrate. This decoupling creates a Temporal Side-Channel Gap. Legacy hardware—including standard Co-Packaged Optics (CPO) and traditional PCB architectures—operates on probabilistic clock-and-data recovery (CDR). This creates a Negative Certification state where the software claims security while the physical layer remains vulnerable to quantum-scale temporal hijacking.

​III. SUMMARY OF THE INVENTION: THE DISCOVERY LOGIC

​The invention is a Deterministic Logic Machine integrated into the communication substrate. It replaces probabilistic digital sampling with a Wave Union interaction.

​The Core Discovery Logic:

​Substrate-Anchored Timing: The invention establishes the physical lattice and dielectric properties of the substrate as the absolute temporal reference, rather than an external electronic clock.

​Pulse-Phase Vernier Carry: Logic is executed by the interaction of multiple pulse-phases. This "Vernier Scale" effect in the temporal domain allows the system to validate signal integrity with sub-picosecond resolution.

​Wave Union Interference Deletion: The invention utilizes the principle of superposition to physically nullify signals that do not match the substrate-anchored timing. Non-coherent signals are ignored via zli interface or truncated.

​IV. HARDWARE TYPE INTEGRATIONS

​The SI-PQC Logic is designed for heterogeneous integration across the following hardware types:

​Refractory Bedding Types: high density high dissipation materials (Scandium Tungsten, vitrimer) to stabilize the Wave Union against thermal drift.

​Liquid-Phase Interface Types: Environments utilizing high-mobility elements (e.g., Gallium) to enhance Direct-Point Sensitivity for pulse detection.

​Field-Effect Integration Types: Substrates incorporating 2D materials (e.g., Graphene) to translate substrate-anchored phase changes into high-speed logic states.

​Stabilized Dielectric Types: Architectures utilizing self-healing or dynamic covalent networks (e.g., Vitrimers) to maintain the geometric precision required for the Interference Ring Deletion.

Copyright Nathan M Allen

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