Ultra-Low Latency Cryptography Areion

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Table of Contents

1. Introduction

The recent evolution of communication technologies demands cryptographic primitives that can offer both robust security and high efficiency. Wide-block ciphers, which operate on larger block sizes than traditional block ciphers, have gained attention as a promising solution to address the limitations of 128-bit block sizes, such as those in AES-GCM. Notably, concerns regarding the limitations of 128-bit block sizes have been raised in public comments[PublicCommentOnSP800-38A] on NIST SP800-38A[SP800-38A].¶

Areion is a novel cryptographic primitive designed to meet these requirements, offering a wide-block permutation suitable for various cryptographic constructions.¶

Areion's design is deeply influenced by the AES instructions and the Single Instruction, Multiple Data (SIMD) paradigm. The AES-NI instruction set, which is a part of modern CPUs, provides hardware support for AES operations. This hardware acceleration is crucial for Areion, enabling it to achieve low-latency operations.¶

In this document, we specify a detailed specification of permutation on Areion.¶

Note: While Areion can be applied for hashing, this document focuses on its encryption capabilities. Hashing functions using Areion are outside of scope in this document.¶

2. Design of Areion Permutation

The Areion permutation algorithm is designed to provide a robust foundation for cryptographic constructions. This section provides a detailed specification of the Areion permutation algorithm for both Areion-256 and Areion-512.¶

For each round r from 1 to 10
    a. L' = L ^ F_0(R)
    b. R' = R ^ F_1(L ^ F_0(R))
    c. Update L = L' and R = R'

For each round r from 1 to 15:
    a. A' = A ^ F_2(D)
    b. B' = B ^ F_3(C ^ F_2(D))
    c. C' = C ^ F_0(B ^ F_3(C ^ F_2(D)))
    d. D' = D ^ F_1(A ^ F_0(B ^ F_3(C ^ F_2(D))))
    e. Update A = A', B = B', C = C', and D = D'

3. Permutation-based AEAD schemes by Areion

The Areion can be constructed as AEADs by combining it with various permutation-based AEAD. In this document, we describe an Areion-OPP as concrete example in Appendix A¶

4. IANA Considerations

This document has no IANA actions.¶

5. Security Considerations

For security considerations of Areion, this document refers to Section 5 of [Areion].¶

6. Acknowledgements

These research results were obtained from the commissioned research(No.05801) by National Institute of Information and Communications Technology (NICT) , Japan.¶

The authors would like to thank Takanori Isobe, Ryoma Ito, Fukang Liu, Kazuhiko Minematsu, Motoki Nakahashi, Kosei Sakamoto, and Rentaro Shiba for their academic insights and advice as a design team on Areion.¶

Appendix A. Permutation-based authenticated encryption modes, OPP

In this section, we describe the algorithm for Areion-OPP. For details, see [Areion]. Note: We plan to describe our Internet Draft based on Section 4.2.2 of [Areion].¶

(TBD)¶

Appendix B. Example Implementation

(TBD)¶

Appendix C. Test Cases & Test Vectors

(TBD)¶

Authors' Addresses