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Requirements for Edge-to-Edge Emulation of Time Division Multiplexed (TDM) Circuits over Packet Switching Networks
RFC 4197

Network Working Group                                          M. Riegel
Request for Comments: 4197                                    Siemens AG
Category: Informational                                     October 2005

              Requirements for Edge-to-Edge Emulation of
             Time Division Multiplexed (TDM) Circuits over
                       Packet Switching Networks

Status of This Memo

   This memo provides information for the Internet community.  It does
   not specify an Internet standard of any kind.  Distribution of this
   memo is unlimited.

Copyright Notice

   Copyright (C) The Internet Society (2005).

Abstract

   This document defines the specific requirements for edge-to-edge
   emulation of circuits carrying Time Division Multiplexed (TDM)
   digital signals of the Plesiochronous Digital Hierarchy as well as
   the Synchronous Optical NETwork/Synchronous Digital Hierarchy over
   packet-switched networks.  It is aligned to the common architecture
   for Pseudo Wire Emulation Edge-to-Edge (PWE3).  It makes references
   to the generic requirements for PWE3 where applicable and complements
   them by defining requirements originating from specifics of TDM
   circuits.

Riegel                       Informational                      [Page 1]
RFC 4197                 PWE3 TDM Requirements              October 2005

Table of Contents

   1. Introduction ....................................................3
      1.1. TDM Circuits Belonging to the PDH Hierarchy ................3
           1.1.1. TDM Structure and Transport Modes ...................4
      1.2. SONET/SDH Circuits .........................................4
   2. Motivation ......................................................5
   3. Terminology .....................................................6
   4. Reference Models ................................................7
      4.1. Generic PWE3 Models ........................................7
      4.2. Clock Recovery .............................................7
      4.3. Network Synchronization Reference Model ....................8
           4.3.1. Synchronous Network Scenarios ......................10
           4.3.2. Relative Network Scenario ..........................12
           4.3.3. Adaptive Network Scenario ..........................12
   5. Emulated Services ..............................................13
      5.1. Structure-Agnostic Transport of Signals out of the
           PDH Hierarchy .............................................13
      5.2. Structure-Aware Transport of Signals out of the
           PDH Hierarchy .............................................14
      5.3. Structure-Aware Transport of SONET/SDH Circuits ...........14
   6. Generic Requirements ...........................................14
      6.1. Relevant Common PW Requirements ...........................14
      6.2. Common Circuit Payload Requirements .......................15
      6.3. General Design Issues .....................................16
   7. Service-Specific Requirements ..................................16
      7.1. Connectivity ..............................................16
      7.2. Network Synchronization ...................................16
      7.3. Robustness ................................................16
           7.3.1. Packet loss ........................................17
           7.3.2. Out-of-order delivery ..............................17
      7.4. CE Signaling ..............................................17
      7.5. PSN Bandwidth Utilization .................................18
      7.6. Packet Delay Variation ....................................19
      7.7. Compatibility with the Existing PSN Infrastructure ........19
      7.8. Congestion Control ........................................19
      7.9. Fault Detection and Handling ..............................20
      7.10. Performance Monitoring ...................................20
   8. Security Considerations ........................................20
   9. References .....................................................20
      9.1. Normative References ......................................20
      9.2. Informative References ....................................21
   10. Contributors Section ..........................................22

Riegel                       Informational                      [Page 2]
RFC 4197                 PWE3 TDM Requirements              October 2005

1.  Introduction

   This document defines the specific requirements for edge-to-edge
   emulation of circuits carrying Time Division Multiplexed (TDM)
   digital signals of the Plesiochronous Digital Hierarchy (PDH) as well
   as the Synchronous Optical NETwork (SONET)/Synchronous Digital

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